As disclosed in the parent U.S. patent application Ser. No. 11/976,925, and U.S. Pat. Nos. 7,459,933 and 7,302,513, which are each incorporated by reference in their entirety, crossbar circuit architectures including programmable impedance states may provide for storage of data used in image and pattern processing. The present patent application provides further embodiments of such systems directed to neural interfaces.
In the past few years there has been an increasing interest in the development of computer/machine interfaces capable of detecting or stimulating mental states. These interfaces may be formed either via arrays of electrodes which are implanted in vivo to serve as a neural interface or via arrays of in vitro electrodes provided externally. Examples of prior art in this area include Gliner et al. U.S. Pat. No. 7,483,747 and Le et al. U.S. Patent Application 2007/0060831. A variety of diverse applications have been proposed for these types of neural interfaces including control of a motorized prosthesis such as a robotic limb, a video gaming controller, or the treatment of neural disorders. However, due to the large range of electrical patterns which the human brain can produce, it can become a difficult computational problem to classify the number of useful detectable patterns for such a neural interface. Solutions based on microprocessors are reliant on software which usually requires retrieval from a memory. Such memory retrieval can be time consuming and reduce the real-time responsiveness of the neural interface. Solutions based on application specific electronic hardware are also possible. However, such solutions can be limited in the number of possible thought patterns that can be identified and in the adaptability to new thought patterns.